The present invention relates to a semiconductor integrated circuit device and, more particularly, to both a semiconductor memory device to be suitably used as a PROM (i.e., Programmable Read Only Memory) and a method of testing the same.
The following method is conceivable as a method of testing deterioration of data retention of an EPROM (Erasable and Programmable ROM). Data are temporarily written (or charges are injected into) in all the bits of a memory thereby to set the individual bits to "0" (all "0"). The bit is then held at a high temperature such as 150.degree. C for some time. After this, all the bits are read out to detect those memory cells where the data "0" have been changed to data "1" (i.e., the state in which no charge is injected nor stored). By this detection, defective bits can be identified. The method described above is based upon the following principle. It is here assumed that a defect or the like has occurred in insulating films between the substrate and floating gate or between the floating gate and the control gate. The charges (e.g., negative charges for an N-channel MOSFET), which are injected into (or stored in) the floating gate by the writing operation, are caused to migrate through the aforementioned defect into the control gate or another portion as a result of it having been held at a high temperature. As a result, the charges are lost (or discharged) to induce a state in which no writing has been conducted.
This method is effective for an EPROM in which written data is erased by being irradiated with ultraviolet rays or the like even after it has been sealed. Despite this advantage, however, the method cannot be applied as it is to the OTP (i.e., One Time Programmable) type EPROM which has been proposed recently. This OTP type EPROM is intended to simplify its product structure and reduce its production cost by packaging an EPROM chip with plastics or the like. As a result, the data cannot be erased once it has been written in the EPROM element which has been sealed for packaging Therefore, the aforementioned method presuming the writing operation of all bits cannot be adopted after the EPROM chip has been packaged and sealed.
By the above reasoning, the OTP type EPROM requires another testing m'ethod such as a method by which the aforementioned test is conducted in a wafer state, for example, so that the EPROM is sealed up after erasure with ultraviolet rays. Meanwhile, however, it is desirable that the aforementioned test be conducted after sealing, because inferior data retention of the EPROM occurs to some degree after the sealing step.
The OTP type EPROM is exemplified by the HN482764P-3, which is disclosed in "HITACHI IC MEMORY DATA BOOK", pp. 263, issued by Hitachi, Ltd., in May, 1984.